瑞斯克石英晶体振荡器说明书，随着电子行业的产品越来越多元化，为了更好顺应市场的变化，Crystek公司利用自身的优势，针对目前振动器产品进行深入研究与探索说明，并研发设计出极具有价值的石英晶体振荡器，并因此吸引了广泛用户的关注，产品融合的高质量低抖动低电压的特点，可以满足不同应用程序的需求，同时也优化相噪声，又获得极好的用户体验。

图1中的皮尔斯门振荡器得到了大多数设计师的认可，但很少有人了解如何正确指定晶体。拓扑结构中使用的晶体图1可以是基本的AT-CUT或BT-CUT。BT-CUT晶体质量差与AT-CUT相比，频率随温度的稳定性。此拓扑使用平行晶体而不是串联晶体。当指定平行晶体时，晶体制造商还将要求您指定负载电容。

要了解负载电容，请考虑串联LC电路，其中晶体是L，负载电容是C。谐振LC电路的频率将作为L和C的函数而变化在晶体情况下，L是固定的（温度不是参数）。瑞斯克石英晶体振荡器说明书.

晶体数据表上的参数由负载电容是25°C时中心频率的公差或校准。如果有源晶体振荡器电路设计不匹配负载电容值，则中心频率将不在数据表的公差限制。有趣的是并联晶体要求其电容负载有效串联其端子。
那么，您的皮尔斯门振荡器向结晶如图2所示的一个简单计算将告诉您。

图2中大多数设计师忽略的最重要的事实是反相器门的内部输入和输出电容。这些与外部（C1和C2）相比在值上是显著的。如果Cin和Cout没有指定，那么每个5 pF的猜测值是好的开始以后可以通过改变启动来优化电路C1和C2的值。所以，不要放弃你的主要宽容；计算您的振荡器电容负载。

既然你知道了如何计算负载电容电路呈现给水晶，您应该选择什么负载电容？在回答这个问题之前，你需要知道晶体中心频率对负载的灵敏度电容。这被称为微调灵敏度S，由下式给出：

其中Cm是晶体的运动电容，
Co是晶体的分流电容，
Cload是负载电容。
从修剪灵敏度方程中，你可以看到，你制作的Cload越小，就越大微调灵敏度。换句话说，如果你正在设计一个固定频率的时钟，那么你选择一个高的Cload值，比如20 pF。但是，如果你正在设计一个可变频率振荡器（VCXO）选择诸如14pF的低Cload值。瑞斯克石英晶体振荡器说明书.

The Pierce-gate oscillator of Figure 1 is well recognized by most designers, but few Tunderstand how to specify the crystal correctly. The crystal used in the topology of Figure 1 can be either a fundamental AT-CUT or BT-CUT. A BT-CUT crystal has poor frequency stability over temperature compared to an AT-CUT. This topology uses a parallel crystal and not a series crystal. When a parallel crystal is specified, the crystal manufacturer will also require that you specify a load capacitance.

To understand load capacitance, think of a series LC circuit where the crystal is the L and the load capacitance is the C. The resonance frequency of the LC circuit will vary as a function of L and C. But in the crystal case, the L is fixed (temperature not being a parameter).

The parameter on the crystal data sheet that is controlled by the load capacitance is the tolerance or calibration of the center frequency at 25°C. If the oscillator circuit is not designed to match the load capacitance value, then the center frequency will not be within the tolerance limits of the data sheet. Interestingly enough, a so-called parallel crystal requires its capacitive load effectively be in series with its terminals.

So what load is your Pierce-gate oscillator presenting to the crystal? A simple calculation illustrated with Figure 2 will tell you.

Cload = {[Cin+C1][C2+Cout]/[Cin+C1+C2+Cout]} + pcb strays (2~3pF)

Example: Let Cin = Cout = 5pF

; C1 = C2 = 20pF Therefore, Cload = {[25][25]/[25+25]} + 3

= 12.5 + 3 = 15.5pF Select Cload = 16pF
The most important fact in Figure 2 that most designers neglect is the internal input and output capacitance of the inverter gate. These are significant in value compared to the external (C1 and C2). If Cin and Cout are not specified, then a guess value of 5 pF for each is a good start. The circuit can be later optimized by changing the starting values of C1 and C2. So don’t throw away your major tolerance; calculate your oscillator capacitive load.

Now that you know how to calculate the load capacitance the circuit presents to the crystal, what load capacitance should you choose? Before answering this question, you need to know the sensitivity of the crystal center frequency vs. load capacitance. This is known as the trim sensitivity S and is given by:

S C C C m o load = − + ⋅ − 2 10 2 6 ( ) in ppm/pF

where Cm is the motional capacitance of the crystal,

Co is the shunt capacitance of the crystal,

and Cload is the load capacitance.

From the trim sensitivity equation you can see that the smaller you make Cload, the larger the trim sensitivity. In other words, if you are designing a fixed frequency clock, then you choose a high Cload value like 20 pF. However, if you are designing a variable frequency oscillator (VCXO), choose a low Cload value such as 14 pF.

The C1 and C2 values also affect the gain of the oscillator. The lower the values, higher the gain. Likewise, C2/C1 ratio also affects gain. To increase the gain, make C1 smaller than C2.